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Futurewei
Technologies, Inc. (Huawei US R&D Center)
Plano, TX
Sr.
Hardware Systems
Architect
December, 2011 – Present
q Analyzed Microsoft SQL Server appliance hardware architectures,
including Fast Track Data Warehouse (FTDW) and Parallel Data Warehouse
(PDW). Jointly proposed the architectures and configurations of Huawei SQL
Server FTDW and PDW, taking advantage of Huawei’s hardware strength.
Studied SQL Server best practices and conducted initial FTDW benchmark
testing based on Microsoft Reference Point software. Directed the follow-on
FTDW testing in Shenzhen, China.
q Studied and analyzed the open source framework Hadoop (HDFS and
MapReduce) for Big Data analytics applications, with an emphasis on the
hardware requirements and opportunities for hardware acceleration,
especially in storage and networking.
GENBAND /
Tekelec / Santera Systems Inc.
Plano, TX
Sr.
Manager of Hardware
Engineering
August, 2005 – November, 2011
q Managed the hardware development of GENBAND G9/8000 media gateways,
including hardware architecture, chassis, circuit boards, and
firmware/driver. Responsible for resource planning, schedule creation and
tracking, coordination of hardware and software integration, compliance
testing such as NEBS-3, and team coaching. Significant amount of sustaining
engineering / product support was also involved.
q Technically guided the hardware development team in Plano, TX and
the offshore development team in Shanghai, China. Coordinated the
communications between the hardware team in Shanghai and the larger
development community in Plano, TX.
q Led the development of the enhanced airflow chassis for G9 media
gateway, with updated fan trays and associated sheet metals, to fully
support the 3rd generation DSP
blades equipped with Mindspeed Comcerto 5000 SoC and the new 10GbE line
cards. The enhanced 14RU chassis supports a system power consumption of
over 3,000 Watts.
q Defined the hardware architecture of the 3rd generation system controller and Ethernet
fabric of G9 (PAC3). Selected Freescale 8-core QorIQ PowerPC and Fulcrum
72-port FocalPoint 10GbE switch with built-in 10GBASE-KR SerDes (which was
later replaced by Broadcom StrataXGS Trident switch due to Fulcrum’s
delayed release). Jointly defined hardware feature requirements and handed
over the detailed hardware design and verification to the offshore team in
Shanghai.
q Hardware architect of the border gateway function (BGF) of G9.
Primary hardware designer of the 10GbE (or 8-port GbE) line card of G9,
which was the key circuit board for BGF. Key components include Cavium
Networks Octeon II 16-core MIPS64 processor, Freescale dual-core QorIQ
PowerPC, DDR3 VLP-RDIMM, Broadcom 24-port GbE Switch with 10GbE uplinks,
Broadcom 10GBASE-T PHY, Applied Micro 10GBASE-LRM PHY, and Xilinx FPGA.
Responsible for architecture definition, detailed design specification,
schematic capture, Signal Integrity (SI) simulation, directing PCB layout,
FPGA coding, and prototype verification.
q Designed the 2-port GbE line card of G9 called GEI-2. Key components
include LSI/Agere APP340 Network Processor with DDR2 memories, Applied
Micro PowerPC 405GPr, Marvell 16-port GbE Switch, and Altera FPGA. The
board was fully functional and released to production at Rev 1.
q Designed the OC-3c/OC-12c ATM line card of G9, which supports two
OC-12c or eight OC-3c ATM interfaces. The card has all the key components
of the GEI-2 card, with the addition of ATM over SONET framer, SONET Clock
and Data Recovery circuit (CDR), and SONET clock synthesizer.
q Designed the universal E1/T1 TDM interface card of G9. It is a cost
reduction design for the previous generation and also features programmable
E1/T1 termination as well as enhanced channel associated signaling (CAS)
capabilities.
q Studied PICMG ATCA, AMC, and MicroTCA standards for future platforms
and new cards on existing platforms.
Sr.
Hardware Design
Engineer
June, 1999 – July, 2005
q Cost reduction design of the Packet Matrix mezzanine card for the
20Gb/s ATM switch fabric of SanteraOne media gateway (GENBAND/Tekelec
8000). The primary change was to reduce the number of FPGAs and
migrate Xilinx Virtex-E FPGAs to less expensive Spartan-IIE family.
Utilized Xilinx ISE Floorplanner to manually place timing critical logic
inside certain Spartan-IIE FPGAs to achieve the same performance as
Virtex-E. PCB placement was also fine tuned to improve timing margin.
q Sustained the SanteraOne Packet Matrix base board with 10Gb/s
switching capacity. The ATM switch fabric is based on MMC Networks' AF5500
chipset with a shared memory virtue output queuing architecture. Maintained
multiple FPGA designs, including backplane interface logic for cell header
and payload multiplexing, message buffer and common memory address
generation logic, and sub-port scheduler for the Per Flow Scheduler device.
q Designed the DS3/OC-3c/OC-12c ATM line card of SanteraOne. It is
consisted of ATM over SONET (or DS3) framers, and ATM switch fabric
interface devices (PIF2) from MMC Networks.
q Designed the OC-3/DS3 TDM interface card of SanteraOne. Agere
SuperMapper was selected as the OC-3/DS3/DS1/E1 framer/multiplexer.
Designed FPGAs for TDM highway multiplexing, RBS/CAS extraction, FDL
processing, and proprietary backplane CPU bus interface. Lead designer of
the backplane redundancy bus of a 1:N equipment protection scheme for the
DS3 interfaces. Key contributor to the DS3 1:N redundancy cable assembly
design.
q Designed the E1/T1 TDM interface card of SanteraOne with Infineon
QuadFALC. Co-inventor of a patented 1:N equipment protection method
that enables in-service replacement of failed cards, which is consisted of
a backplane redundancy bus and a E1/T1 redundancy cable assembly.
SanCom
Technology, Inc.
Austin, TX
Hardware
Design
Engineer
December, 1997 – May, 1999
q Designed the OC-3c/OC-12c ATM line card of AS-850 ATM access
concentrator. There is also a Bellcore GR-1244 compliant Stratum-3 network
timing module on the card to provide timing to the AS-850 system.
q Designed the T1/E1 TDM interface card of AS-850. Infineon QuadFALC
was selected as the T1/E1 LIU/framer combo.
q Designed the Network Clock Controller of CS-1000 ATM switch, which
includes a Stratum-3 network timing module, BITS interface, and an HDLC
controller for the SS-7 link.
Harris
Communications (Shenzhen) Ltd.
Shenzhen, China
Hardware
Design
Engineer
November, 1996 – November, 1997
q Designed the radio processor card of MicroStar Plus 7/8GHz digital
microwave communication system (radio). It was the control card of the
outdoor unit, with a Motorola MC68HC11 micro-controller.
q Architected the order-wire service card of the Constellation
radio. The building blocks of the card are PCM CODECs, voice bridges,
signaling unit, and PCM voice channel multiplexer.
Huawei
Technologies Company, Ltd.
Shenzhen, China
Firmware
Engineer
August, 1996 – October, 1996
q Maintained the firmware of the MSU (Multiple Subscriber Unit) RF
channel board in a wireless local loop (WLL) system. The micro-controller
is NEC uPD78054, and the primary function of the software is to process the
wireless channel associated signaling.
Tsinghua
University
Beijing, China
Research
Assistant
June, 1993 – June, 1996
q Designed the multi-channel digital baseband receive shaping filter
for a satellite on-board processing system. A TI TMS320C25 DSP was utilized
to implement the four-channel receive matched filtering by means of
time-division processing. Also designed the multi-channel pi/4-DQPSK
modulator on the same card. TI TMS320C25 was utilized to implement the
four-channel poly-phase FIR interpolation filtering for the transmit pulse
shaping.
q Designed the digital baseband transmit shaping filter for the QPSK
modem of a VSAT (Very Small Aperture Terminal) system. A ROM-based look-up
table was utilized to implement the transmit pulse shaping.
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